1. Field of the Invention
The present invention relates to a semiconductor device and a method of forming the same and, more particularly, to a cell array of a semiconductor memory and a method of forming the same.
A claim of priority is made to Korean Patent Application No. 10-2005-0076884 filed Aug. 22, 2005, in the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.
2. Description of the Related Art
A semiconductor device may be configured for high density integration by reducing the line widths of word lines and selection lines that are formed on a cell array. Specifically, in NAND semiconductor memory devices, where a plurality of word lines are disposed between the selection lines to constitute a cell string, the line widths of word lines can be reduced. However, the extent to which the line widths of the word lines can be reduced is limited because of limitations in the photolithography process. Moreover, there are factors that would limit the line width reduction of selection lines too. For example, the extent to which the line width of the selection lines forming cell transistors on both sides of the cell string may be reduced is limited because of punch through and leakage current. In particular, the punch through and leakage current may be caused by a short channel effect.
Efforts have been directed to develop methods for reducing the line width of selection lines in a memory cell without reducing the channel length of the selected transistors. One such method involves forming the selected transistors with a recessed channel.
FIG. 1 is a sectional view of a prior art transistor with a recessed channel. Referring to FIG. 1, a gate electrode 26 is formed on a recess region 10r where a portion of a semiconductor substrate 10 is etched, to form a recessed channel. In addition, a gate insulation layer 20 is conformally formed in the recess region 10r. Specifically, the gate electrode 26 is formed on the gate insulation layer 20. Furthermore, a source/drain region 30 is formed in the semiconductor substrate 10 on both sides of the gate electrode 26. Moreover, a channel is formed on a recessed portion of the semiconductor substrate 10, which is disposed on the bottom of the gate electrode 26. Thus, the width of a channel formed along a curvature of the recessed region 10r is wider than that of the gate electrode 26.
As illustrated in FIG. 1, in a conventional transistor with a recessed channel, the center of the recess region 10r is formed on the center of the gate electrode 26, and the gate electrode 26 and the channel of the transistor are formed in a symmetric structure. In this structure, an aspect ratio of the recess region 10r becomes larger when the width of the gate electrode 26 is reduced. Furthermore, in silicon oxide nitric oxide silicon (SONOS) devices having a multi-layer insulation layer formed on the gate insulation layer 20, an aspect ratio of the recess region 10r becomes larger. The large aspect ratio of the recess region 10r may cause the insulation layers to be non-uniformly formed on the center and the edges of the recess region 10r. The non-uniform formation of the insulation layers may change the characteristics of the memory cell.
The present disclosure is directed towards one or more problems associated with the prior art cell array formation methods.